The art of processor customization: balancing innovation and risk

At every level of electronics, from smartwatches to the cloud, performance efficiency is key. For the past fifty years, Moore’s Law has driven the technology – the ability to double the number of transistors in the same area every two years. Moore’s law in combination with the concepts of Dennard Scaling, the concept that the power density in transistors remains constant, made it possible to do the same calculation in less power and space cost or more performance in the same space, same power and same cost. However, the limitations of traditional Moore’s Law and Dennard Scaling characteristics combined with changes in the dynamics of semiconductor design and manufacturing place an emphasis on optimizing the hardware for the workload, which which increasingly means selecting or even creating the right processing element for the task. . Gone are the days of the big stick – using the latest, fastest and most powerful processor to do it all. Customization at the silicon, packaging, and even instruction set level is now necessary to ensure performance efficiency, but every path comes with tradeoffs.

One of the areas of customization that has become most evident in demonstrating this is the use of specialized functional hardware blocks for critical chip functions such as I/O, power management, security, on-chip networking and even the processing of the workload itself. Due to this specialization, most processors are now bundled with additional hardware features, collectively referred to as system-on-chip (SoC). But even within these hardware functions, the flexibility of the core processing architecture, often referred to as the CPU, is key to maximizing performance efficiency, as well as scalability and reusability. An effective way to achieve this goal is to use custom instructions. Configurable microprocessor architectures that support this level of customization include Synopsys ARC, RISC-V, and Cadence Tensilica processors.

Often grouped with the Arm architecture as “processor cores”, configurable processor cores offer customization options not available with the Arm architecture. Arm CPU IP cores provide the same instruction set to everyone, which provides software compatibility between SoC designs, but does not allow for the addition of custom instructions that increase execution and efficiency of performance for specific functions or algorithms. Arm architectural licenses that allow this level of customization are available, but these licenses are generally limited to high-performance applications such as servers where volume and margins can justify the investment. Architecture licensing also requires additional customer expertise because Arm has not designed its processors to be customized and does not provide the specialized tools needed to implement customization.

Synopsys ARC, RISC-V, and Cadence Tensilica processors were designed to support custom instructions from scratch, which means it’s practical to adapt these cores for SoCs designed even for embedded/IoT applications who can perform very limited tasks. Even optimizing these tasks can improve performance and/or reduce power consumption. Customization requires software tools to map code to custom instructions. Due to the open structure of RISC-V International, the tools are provided by the community, including universities and other developers. However, the RISC-V ISA and the tools are relatively new. On the other hand, the Synopsys ARC architecture has been available for 27 years and has been widely used as a power-efficient processing solution in billions of common consumer and embedded applications, such as all the first Wi-Fi interfaces of the first Intel Centrino. mobile PC platforms.

The ARC architecture is a family of IP processors, many of which are optimized for specific types of applications, such as low-power, security-critical, high-security, high-throughput, high-performance, and even inference processing. AI. All of these applications benefit from personalized instructions. Additionally, because it is under the Synopsys Intellectual Property (IP) umbrella, the Synopsys ARC architecture is supported by some of the industry’s most advanced software programming tools and complementary IP.

One of the challenges of designing a new chip or electronics platform is finding a balance between innovation and risk. Innovation in the form of full customization can deliver performance benefits and differentiation at the risk of reducing intellectual property reusability, limiting design performance scalability, and increasing time to market. the market and the costs of new products. On the other hand, reducing risk through full standardization can limit differentiation and, more importantly, limit performance efficiency.

It is important to select the right processing element for the workload and to use customization selectively where it provides the most benefit. As a result, SoCs in many applications are increasingly using a mix of processing architectures within a single SoC and even for chips used in multi-chip modules (MCMs)/systems-in-packages (SiPs) designed around specific workload requirements.

Margie D. Carlisle